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1/32 january 2005 M41T62, m41t63 m41t64, m41t65 serial access real-time clock with alarms features summary 350na timekeeping current @ 3v timekeeping down to 1.0v 1.3v to 3.6v i 2 c bus operating voltage counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century serial interface supports i 2 c bus (400khz) programmable alarm with flag bit only (m41t63/64) programmable alarm with flag bit and interrupt function (M41T62/65) low operating current of 35a software clock calibration oscillator stop detection 32khz square wave on power-up (M41T62/63/64) watchdog timer watchdog output (m41t63/65) automatic leap year compensation operating temperature of ?40 to 85c lead-free 16-pin qfn package figure 1. package table 1. device options qfn16 (q) basic rtc alarms osc fail detect watchdog timer calibration sqw output irq output wdo output f 32k output M41T62 ??? ? ? ?? m41t63 ??? ? ? ? ? m41t64 ??? ? ? ? ? m41t65 ??? ? ? ??
M41T62/63/64/65 2/32 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 1. device options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. M41T62 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. m41t64 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. m41t63 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 5. m41t65 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 6. M41T62 16-pin qfn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 7. m41t63 16-pin qfn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 8. m41t64 16-pin qfn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 9. m41t65 16-pin qfn connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 10.M41T62 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 11.m41t63 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 12.m41t64 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 13.m41t65 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 14.hardware hookup for battery back-up operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2-wire bus characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 15.serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 16.acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 17.slave address location. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 18.read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 19.alternative read mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 20.write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 timekeeper? registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. M41T62 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 4. m41t63 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 table 5. m41t64 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 6. m41t65 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 calibrating the clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3/32 M41T62/63/64/65 figure 21.crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 22.calibration waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 setting alarm clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 23.alarm interrupt reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7. alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 watchdog output (wdo - m41t63/65 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 square wave output (M41T62/63/64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8. square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 full-time 32khz square wave output (m41t64). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 century bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 output driver pin (M41T62/65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 oscillator stop detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 initial power-on defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9. initial power-on default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10. century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24.ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25.crystal isolation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 15. crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 16. oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 26.bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 27.qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, outline . . . . . . . . 28 table 18. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, mechanical data . 29 figure 28.qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm, recommended footprint . . 29 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 19. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
M41T62/63/64/65 4/32 summary description the m41t6x serial access timekeeper ? is a low power serial rtc with a built-in 32.768 khz oscillator (external crystal controlled). eight regis- ters (see table 3., page 14 ) are used for the clock/ calendar function and are configured in binary coded decimal (bcd) format. an additional 8 reg- isters provide status/control of alarm, 32khz out- put, calibration, and watchdog functions. addresses and data are transferred serially via a two line, bi-directional i 2 c interface. the built-in address register is incremented automatically af- ter each write or read data byte. functions available to the user include a time-of- day clock/calendar, alarm interrupts (M41T62/65), 32khz output (m41t64), programmable square wave output (M41T62/63/64), and watchdog out- put (m41t63/65). the eight clock address loca- tions contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour bcd format. corrections for 28- , 29- (leap year), 30- and 31-day months are made automatically. the m41t6x is supplied in a 16-pin qfn. figure 2. M41T62 logic diagram note: 1. open drain. 2. defaults to 32khz on power-up. figure 3. m41t64 logic diagram note: 1. open drain. 2. defaults to 32khz on power-up. figure 4. m41t63 logic diagram note: 1. open drain. 2. defaults to 32khz on power-up. figure 5. m41t65 logic diagram note: 1. open drain. scl v cc M41T62 v ss sda irq/out (1) sqw (2) xi xo ai09103 scl v cc m41t64 v ss sda f 32k (2) sqw (1) xi xo ai09108 scl v cc m41t63 v ss sda wdo (1) sqw (2) xi xo ai09189 scl v cc m41t65 v ss sda wdo (1) irq/ft/out (1) xi xo ai09109
5/32 M41T62/63/64/65 figure 6. M41T62 16-pin qfn connections note: 1. sqw output will default to 32khz upon power-up. 2. open drain. figure 7. m41t63 16-pin qfn connections note: 1. sqw output will default to 32khz upon power-up. 2. open drain. figure 8. m41t64 16-pin qfn connections note: 1. enabled on power-up. 2. open drain. figure 9. m41t65 16-pin qfn connections note: 1. open drain. table 2. signal names 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo sqw (1) v ss v ss v cc nc scl sda irq/out (2) ai09100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo sqw (1) v ss v ss v cc nc scl sda wdo (2) ai09190 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo f 32k (1) v ss v ss v cc nc scl sda sqw (2) ai09101 xi oscillator input xo oscillator output sda serial data input/output scl serial clock input irq /out interrupt or out output (open drain) irq /ft/ out interrupt, frequency test, or out output (open drain) sqw programmable square wave - defaults to 32khz on power-up (open drain for m41t64 only) f 32k dedicated 32khz output (m41t64 only) wdo watchdog timer output (open drain) v cc supply voltage v ss ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc nc nc nc nc nc xi xo wdo (1) v ss v ss v cc nc scl sda irq/ft/out (1) ai09102
M41T62/63/64/65 6/32 figure 10. M41T62 block diagram note: 1. open drain. 2. defaults to 32khz on power-up. figure 11. m41t63 block diagram note: 1. open drain. 2. defaults to 32khz on power-up. figure 12. m41t64 block diagram note: 1. defaults enabled on power-up. 2. open drain. real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog irq/out (1) sqw (2) ofie sda scl afe sqwe i 2 c interface 32khz oscillator xtal ai08899a real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog sqw (2) wdo (1) sda scl sqwe i 2 c interface 32khz oscillator xtal ai09191 real time clock calendar rtc w/alarm oscillator fail detect square wave watchdog sqw (2) f 32k (1) 32ke sda scl sqwe i 2 c interface 32khz oscillator xtal ai09192
7/32 M41T62/63/64/65 figure 13. m41t65 block diagram note: 1. open drain. figure 14. hardware hookup for battery back-up operation note: 1. diode required on open drain pin (m41t65 only) for battery (or supercap) back-up. low threshold bat42 diode recommended. 2. for M41T62 and m41t65 (open drain). 3. for m41t63 and m41t65 (open drain). 4. for m41t64 (open drain). real time clock calendar rtc w/alarm oscillator fail detect watchdog irq/ft/out (1) wdo (1) ofie sda scl ft afe i 2 c interface 32khz oscillator xtal ai09193 ai10400 v cc port reset input sqwin serial clock line serial data line 32khz clkin xo xi m41t6x mcu v ss irq/ft/out (2) wdo (3) sqw (4) f 32k sda scl v cc v cc (1)
M41T62/63/64/65 8/32 operation the m41t6x clock operates as a slave device on the serial bus. access is obtained by implementing a start condition followed by the correct slave ad- dress (d0h). the 16 bytes contained in the device can then be accessed sequentially in the following order: 1. tenths/hundredths of a second register 2. seconds register 3. minutes register 4. hours register 5. square wave/day register 6. date register 7. century/month register 8. year register 9. calibration register 10. watchdog register 11 - 15. alarm registers 16. flags register 2-wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bi-direction- al data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. ? changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy. both data and clock lines remain high. start data transfer. a change in the state of the data line, from high to low, while the clock is high, defines the start condition. stop data transfer. a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. data valid. the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowl- edges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? the device that controls the message is called ?master.? the de- vices that are controlled by the master are called ?slaves.?
9/32 M41T62/63/64/65 acknowledge. each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. a slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low dur- ing the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 15. serial bus data transfer sequence figure 16. acknowledgement sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
M41T62/63/64/65 10/32 read mode in this mode the master reads the m41t6x slave after setting the slave address (see figure 18., page 11 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. next the start condition and slave ad- dress are repeated followed by the read mode control bit (r/w =1). at this point the master trans- mitter becomes the master receiver. the data byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t6x slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to the slave transmitter. the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). t he update will resume due to a stop condition or when the pointer increments to any non-clock address (08h-0fh). note: this is true both in read mode and write mode. an alternate read mode may also be implement- ed whereby the master reads the m41t6x slave without first writing to the (volatile) address point- er. the first address that is read is the last one stored in the pointer (see figure 19., page 11 ). figure 17. slave address location ai00602 r/w slave address start a 01000 11 msb lsb
11/32 M41T62/63/64/65 figure 18. read mode sequence figure 19. alternative read mode sequence ai00899 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address s start r/w slave address ack ai00895 bus activity: ack s ack ack ack no ack stop start p sda line bus activity: master r/w data n data n+1 data n+x slave address
M41T62/63/64/65 12/32 write mode in this mode the master transmitter transmits to the m41t6x slave receiver. bus protocol is shown in figure 20., page 12 . following the start con- dition and slave address, a logic '0' (r/w =0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on-chip address pointer. the data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the m41t6x slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see figure 17., page 10 and again after it has re- ceived the word address and each data byte. figure 20. write mode sequence ai00591 bus activity: ack s ack ack ack ack stop start p sda line bus activity: master r/w data n data n+1 data n+x word address (an) slave address
13/32 M41T62/63/64/65 clock operation the m41t6x is driven by a quartz-controlled oscil- lator with a nominal frequency of 32.768khz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the eight byte clock register (see table 3., M41T62 register map , table 4., m41t63 reg- ister map , table 5., m41t64 register map , and table 6., m41t65 register map ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. tenths/hundredths of seconds, seconds, min- utes, and hours are contained within the first four registers. note: a write to any clock register will result in the tenths/hundredths of seconds being reset to ?00,? and tenths/hundredths of seconds cannot be written to any value other than ?00.? bits d0 through d2 of register 04h contain the day (day of week). registers 05h, 06h, and 07h contain the date (day of month), month, and years. the ninth clock register is the calibration register (this is described in the clock calibration section). bit d7 of register 01h contains the stop bit (st). setting this bit to a '1' will cause the oscil- lator to stop. when reset to a '0' the oscillator re- starts within one second (typical). note: upon initial power-up, the user should set the st bit to a '1,' then immediately reset the st bit to '0.' this provides an additional ?kick-start? to the oscillator circuit. bit d7 of register 02h (minute register) contains the oscillator fail interrupt enable bit (ofie). when the user sets this bit to '1,' any condition which sets the oscillator fail bit (of) (see oscilla- tor stop detection, page 23 ) will also generate an interrupt output. bits d6 and d7 of clock register 06h (century/ month register) contain the century bit 0 (cb0) and century bit 1 (cb1). note: a write to any location within the first eight bytes of the clock register (00h-07h), includ- ing the ofie bit, rs0-rs3 bit, and cb0-cb1 bits will result in an update of the system clock and a reset of the divider chain. this could result in an in- advertent change of the current time. these non- clock related bits should be written prior to setting the clock, and remain unchanged until such time as a new clock time is also written. the eight clock registers may be read one byte at a time, or in a sequential block. provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the read. timekeeper ? registers the m41t6x offers 16 internal registers which contain clock, calibration, alarm, watchdog, flags, and square wave. the clock registers are memory locations which contain external (user ac- cessible) and internal copies of the data (usually referred to as biport ? timekeeper cells). the external copies are independent of internal func- tions except that they are updated periodically by the simultaneous transfer of the incremented inter- nal copy. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address (00h to 07h). the system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). the update will resume ei- ther due to a stop condition or when the pointer increments to a non-clock address. timekeeper and alarm registers store data in bcd format. calibration, watchdog, and square wave bits are written in a binary format.
M41T62/63/64/65 14/32 table 3. M41T62 register map keys: 0 = must be set to '0' af = alarm flag (read only) afe = alarm flag enable flag bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillator fail bit ofie = oscillator fail interrupt enable bit out = output level rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24 hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h out 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
15/32 M41T62/63/64/65 table 4. m41t63 register map keys: 0 = must be set to '0' af = alarm flag (read only) bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillator fail bit rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24 hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h 0 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah 0 sqwe 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
M41T62/63/64/65 16/32 table 5. m41t64 register map keys: 0 = must be set to '0' 32ke = 32khz enable bit af = alarm flag (read only) bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits of = oscillator fail bit rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits rs0-rs3 = sqw frequency bits s = sign bit sqwe = square wave enable bit st = stop bit wdf = watchdog flag bit (read only) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h 0 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24 hour format) hours 00-23 04h rs3 rs2 rs1 rs0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h 0 0 s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah 0 sqwe 32ke al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
17/32 M41T62/63/64/65 table 6. m41t65 register map keys: 0 = must be set to '0' af = alarm flag (read only) afe = alarm flag enable flag bmb0 - bmb4 = watchdog multiplier bits cb0-cb1 = century bits ft = frequency test bit of = oscillator fail bit ofie = oscillator fail interrupt enable bit out = output level rb0 - rb2 = watchdog resolution bits rpt1-rpt5 = alarm repeat mode bits s = sign bit st = stop bit wdf = watchdog flag bit (read only) addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h 0.1 seconds 0.01 seconds 10ths/100ths of seconds 00-99 01h st 10 seconds seconds seconds 00-59 02h ofie 10 minutes minutes minutes 00-59 03h 0 0 10 hours hours (24 hour format) hours 00-23 04h 0 0 0 0 0 day of week day 01-7 05h 0 0 10 date date: day of month date 01-31 06h cb1 cb0 0 10m month century/ month 0-3/01-12 07h 10 years year year 00-99 08h out ft s calibration calibration 09h rb2 bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 0ah afe 0 0 al 10m alarm month al month 01-12 0bh rpt4 rpt5 ai 10 date alarm date al date 01-31 0ch rpt3 0 ai 10 hour alarm hour al hour 00-23 0dh rpt2 alarm 10 minutes alarm minutes al min 00-59 0eh rpt1 alarm 10 seconds alarm seconds al sec 00-59 0fh wdf af 0 0 0 of 0 0 flags
M41T62/63/64/65 18/32 calibrating the clock the m41t6x is driven by a quartz controlled oscil- lator with a nominal frequency of 32,768hz. the accuracy of the real-time clock depends on the frequency of the quartz crystal that is used as the time-base for the rtc. the accuracy of the clock is dependent upon the accuracy of the crystal, and the match between the capacitive load of the oscil- lator circuit and the capacitive load for which the crystal was trimmed. the m41t6x oscillator is de- signed for use with a 6pf crystal load capacitance. when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with tem- perature (see figure 21., page 19 ). therefore, the m41t6x design employs periodic counter correc- tion. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the di- vide by 256 stage, as shown in figure 22., page 19 . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4-d0) in the calibration register (08h). these bits can be set to represent any value be- tween 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates nega- tive calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or le ngthened by 256 oscillator cycles. if a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ?2.034 ppm of adjustment per calibra- tion step in the calibration register. assuming that the oscillato r is running at exactly 32,768 hz, each of the 31 increments in the cali- bration byte would represent +10.7 or ?5.35 sec- onds per day which corresponds to a total range of +5.5 or ?2.75 minutes per month (see figure 22., page 19 ). two methods are available for ascertaining how much calibration a given m41t6x may require: ? the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?timeke eper ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. the designer could provide a simple utility that accesses the calibration byte. ? the second approach is better suited to a manufacturing environment, and involves the use of either the sqw pin (M41T62/63/64) or the irq /ft/out pin (m41t65). the sqw pin will toggle at 512hz when rs3 = '0,' rs2 = '1,' rs1 = '1,' rs0 = '0,' sqwe = '1,' and st = '0.' alternatively, for the m41t65, the irq /ft/ out pin will toggle at 512hz when ft and out bits = '1' and st = '0.' any deviation from 512hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm oscilla- tor frequency error, requiring a ?10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test or square wave output frequency.
19/32 M41T62/63/64/65 figure 21. crystal accuracy across temperature figure 22. calibration waveform ai07888 ?160 0 10203040506070 frequency (ppm) temperature c 80 ?10 ?20 ?30 ?40 ?100 ?120 ?140 ?40 ?60 ?80 20 0 ?20 = ?0.036 ppm/ c 2 0.006 ppm/ c 2 k ? f = k x (t ? t o ) 2 f t o = 25 c 5 c ai00594b normal positive calibration negative calibration
M41T62/63/64/65 20/32 setting alarm clock registers address locations 0ah-0eh contain the alarm set- tings. the alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second, or repeat every year, month, day, hour, minute, or second. bits rpt5?rpt1 put the alarm in the repeat mode of operation. ta- ble 7., page 20 shows the possible configurations. codes not listed in the table default to the once per second mode to quickly alert the user of an incor- rect alarm setting. when the clock information matches the alarm clock settings based on the match criteria defined by rpt5?rpt1, the af (alarm flag) is set. if afe (alarm flag enable) is also set (M41T62/65), the alarm condition activates the irq /out or irq /ft/ out pin. to disable the alarm, write '0' to the alarm date register and to rpt5?rpt1. note: if the address pointer is allowed to incre- ment to the flag register address, an alarm con- dition will not cause the interrupt/flag to occur until the address pointer is moved to a different ad- dress. it should also be noted that if the last ad- dress written is the ?alarm seconds,? the address pointer will increment to the flag address, causing this situation to occur. the irq output is cleared by a read to the flags register as shown in figure 23., page 20 . a sub- sequent read of the flags register is necessary to see that the value of the alarm flag has been reset to '0.' figure 23. alarm interrupt reset waveform table 7. alarm repeat modes rpt5 rpt4 rpt3 rpt2 rpt1 alarm setting 1 1 1 1 1 once per second 1 1 1 1 0 once per minute 1 1 1 0 0 once per hour 11000 once per day 1 0 0 0 0 once per month 00000 once per year alarm flag bit (af) 0fh 0eh 00h high-z ai08898 irq/out or irq/ft/out
21/32 M41T62/63/64/65 watchdog timer the watchdog timer can be used to detect an out- of-control microprocessor. the user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. bits bmb4-bmb0 store a binary multiplier and the three bits rb2-rb0 select the resolution where: 000=1/16 second (16hz); 001=1/4 second (4hz); 010=1 second (1hz); 011=4 seconds (1/4hz); and 100 = 1 minute (1/60hz). note: invalid combinations (101, 110, and 111) will not enable a watchdog time-out. setting the bmb4-bmb0 = 0 with any combination of rb2- rb0, other than 000, will result in an immediate watchdog time-out. the amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (for example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). if the processor does not reset the timer within the spec- ified period, the m41t6x sets the wdf (watchdog flag) and generates an interrupt on the irq pin (M41T62), or a watchdog output pulse (m41t63 and m41t65 only) on the wdo pin. the watchdog timer can only be reset by having the microproces- sor perform a write of the watchdog register. the time-out period then starts over. should the watchdog timer time-out, any value may be written to the watchdog register in order to clear the irq pin. a value of 00h will disable the watchdog function until it is again programmed to a new value. a read of the flags register will re- set the watchdog flag (bit d7; register 0fh). the watchdog function is automatically disabled upon power-up, and the watchdog register is cleared. note: a write to any clock register will restart the watchdog timer. watchdog output (wdo - m41t63/65 only) if the processor does not reset the watchdog timer within the specified period, the watchdog output (wdo ) will pulse low for t rec (see table 17., page 27 ). this output may be connected to the reset input of the processor in order to gener- ate a processor reset. after a watchdog time-out occurs, the timer will remain disabled until such time as a new countdown value is written into the watchdog register. note: the crystal oscillator must be running for the wdo pulse to be available. the wdo output is an n-channel, open drain out- put driver (with i ol as specified in table 14., page 26 ).
M41T62/63/64/65 22/32 square wave output (M41T62/63/64) the M41T62/63/64 offers the user a programma- ble square wave function which is output on the sqw pin. rs3-rs0 bits located in 04h establish the square wave output frequency. these fre- quencies are listed in table 8 . once the selection of the sqw frequency has been completed, the sqw pin can be turned on and off under software control with the square wave enable bit (sqwe) located in register 0ah. the sqw output is an n-channel, open drain out- put driver for the m41t64, and a full cmos output driver for the M41T62/63. the initial power-up de- fault for the sqw output is 32khz (except for m41t64, which defaults disabled). table 8. square wave output frequency full-time 32khz square wave output (m41t64) the m41t64 offers the user a special 32khz square wave function which is enabled on power- up to output on the f 32k pin as long as v cc 1.3v, and the oscillator is running (st bit = '0'). this function is available within one second (typ) of ini- tial power-up and can only be disabled by setting the 32ke bit to '0' or the st bit to '1.' if not used, the f 32k pin should be disconnected and allowed to float. square wave bits square wave rs3 rs2 rs1 rs0 frequency units 0000none? 0 0 0 1 32.768 khz 00108.192khz 00114.096khz 01002.048khz 01011.024khz 0110512hz 0111256hz 1000128hz 100164hz 101032hz 101116hz 11008hz 11014hz 11102hz 11111hz
23/32 M41T62/63/64/65 century bits these two bits will increment in a binary fashion at the turn of the century, and handle all leap years correctly. see table 10., page 23 for additional explanation. output driver pin (M41T62/65) when the ofie bit, afe bit, and watchdog regis- ter are not set to generate an interrupt, the irq / out pin becomes an output driver that reflects the contents of d7 of the calibration register. in other words, when d7 (out bit) is a '0,' then the irq / out pin will be driven low. note: the irq /out pin is an open drain which re- quires an external pull-up resistor. oscillator stop detection if the oscillator fail (of) bit is internally set to a '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date da- ta. this bit will be set to '1' any time the oscillator stops. in the event the of bit is found to be set to '1' at any time other than the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: ? the first time power is applied (defaults to a '1' on power-up). note: if the of bit cannot be written to '1' four (4) seconds after the initial power-up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' ? the voltage present on v cc or battery is insufficient to support oscillation. ? the st bit is set to '1.' ? external interference of the crystal if the oscillator fail interrupt enable bit (ofie) is set to a '1,' the irq pin will also be activated. the irq output is cleared by resetting the ofie or of bit to '0' (not by reading the flag register). the of bit will remain set to '1' until written to logic '0.' the oscillator must start and have run for at least 4 seconds before attempting to reset the of bit to '0.' if the trigger event occurs during a power- down condition, this bit will be set correctly. initial power-on defaults upon application of power to the device, the regis- ter bits will initially power-on in the state indicated in table 9 . table 9. initial power-on default values note: 1. all other control bits power-up in an undetermined state. table 10. century bits examples note: 1. leap year occurs every four years (for years evenly divisible by four), except for years evenly divisible by 100. the on ly exceptions are those years evenly divisible by 400 (the year 2000 was a leap year, year 2100 is not). condition device st of ofie out ft afe sqwe 32ke rs3-1 rs0 watchdog initial power-up (1) M41T62 0 1 0 1 n/a 0 1 n/a 0 1 0 m41t63 0 1 n/a n/a n/a n/a 1 n/a 0 1 0 m41t64 0 1 n/a n/a n/a n/a 0 1 0 1 0 m41t65 0 1 0 1 0 0 n/a n/a n/a n/a 0 cb0 cb1 leap year? example (1) 00yes2000 0 1 no 2100 1 0 no 2200 1 1 no 2300
M41T62/63/64/65 24/32 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 11. absolute maximum ratings note: 1. test conforms to jedec standard. 2. data based on characterization results, not tested in production. 3. reflow at peak temperature of 260c (total thermal budget not to exceed 245c for greater than 30 seconds). sym parameter conditions (1) value (2) unit t stg storage temperature (v cc off, oscillator off) ?55 to 125 c v cc supply voltage ?0.3 to 4.6 v t sld (3) lead solder temperature for 10 seconds 260 c v io input or output voltages ?0.2 to vcc+0.3 v i o output current 20 ma p d power dissipation 1 w v esd(hbm) electro-static discharge voltage (human body model) t a = 25c >1000 v v esd(rcdm) electro-static discharge voltage (robotic charged device model) t a = 25c >1000 v
25/32 M41T62/63/64/65 dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 12. operating and ac measurement conditions note: output hi-z is defined as the point where data is no longer driven. figure 24. ac measurement i/o waveform figure 25. crystal isolation example note: substrate pad should be tied to v ss . table 13. capacitance note: 1. effective capacitance measured with power supply at 3.6v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter m41t6x supply voltage (v cc ) 1.3v to 3.6v ambient operating temperature (t a ) ?40 to 85c load capacitance (c l ) 50pf input rise and fall times 5ns input pulse voltages 0.2v cc to 0.8 v cc input and output timing ref. voltages 0.3v cc to 0.7 v cc ai02568 0.8v cc 0.2v cc 0.7v cc 0.3v cc ai09127 crystal xi xo gnd local grounding plane (layer 2) symbol parameter (1,2) min max unit c in input capacitance 7 pf c out (3) output capacitance 10 pf t lp low-pass filter input time constant (sda and scl) 50 ns
M41T62/63/64/65 26/32 table 14. dc characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 1.3v to 3.6v (except where noted). 2. oscillator start-up guaranteed at 1.5v only. 3. when using battery back-up, v cc fall time should not exceed 10mv/s. table 15. crystal electrical characteristics note: 1. externally supplied if using the qfn16 package. stmicroelectronics recommends the citizen cfs-145 (1.5x5mm) and the kds dt-38 (3x8mm) for thru-hole, or the kds dmx-26s (3.2x8mm) for surface-mount, tuning fork-type quartz crystals. kds can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp . citizen can be contacted at csd@citizen-america.com or http://www.citizencrystal.com . 2. load capacitors are integrated within the m41t6x. circuit board layout considerations for the 32.768khz crystal of minimum tr ace lengths and isolation from rf generating signals should be taken into account. 3. guaranteed by design. sym parameter test condition (1) min typ max unit v cc (3) operating voltage clock (2) 1.0 3.6 v i 2 c bus (400khz) 1.3 3.6 v i cc1 supply current scl = 400khz (no load) 3.6v 50 100 a 3.0v 35 a 2.5v 30 a 2.0v 20 a i cc2 supply current (standby) scl = 0hz all inputs v cc ? 0.2v v ss + 0.2v sqw off 3.6v 375 700 na 3.0v @ 25c 350 na 2.0v @ 25c 310 na v il input low voltage ?0.2 0.3v cc v v ih input high voltage 0.7v cc v cc +0.3 v v ol output low voltage v cc = 3.6v, i ol = 3.0ma (cmos or open drain) 0.4 v v cc = 3.6v, i ol = 1.0ma (sqw, wdo , irq ) 0.4 v v oh output high voltage v cc = 3.6v, i oh = ?1.0ma (push-pull) 2.4 v pull-up supply voltage (open drain) irq /out, irq /ft/out, wdo , sqw (m41t64 only) 3.6 v i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a sym parameter (1,2) min typ max units f o resonant frequency 32.768 khz r s series resistance 65 (3) k ? c l load capacitance 6 pf
27/32 M41T62/63/64/65 table 16. oscillator characteristics note: 1. reference value. t a = 25c, v cc = 3.0v, cmj-145 (c l = 6pf, 32,768hz) manufactured by citizen. figure 26. bus timing requirements sequence table 17. ac characteristics note: 1. valid for ambient operating temperature: t a = ?40 to 85c; v cc = 1.3 to 3.6v (except where noted). 2. transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. symbol parameter conditions min typ max unit v sta oscillator start voltage 10 seconds 1.5 v t sta oscillator start time v cc = 3.0v 1s c g xin 12 pf c d xout 12 pf ic-to-ic frequency variation (1) ?10 +10 ppm sym parameter (1) min typ max units f scl scl clock frequency 0 400 khz t low clock low period 1.3 s t high clock high period 600 ns t r sda and scl rise time 300 ns t f sda and scl fall time 300 ns t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:dat (2) data setup time 100 ns t hd:dat data hold time 0 s t su:sto stop condition setup time 600 ns t buf time the bus must be free before a new transmission can start 1.3 s t rec watchdog output pulse width 96 98 ms ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
M41T62/63/64/65 28/32 package mechanical information figure 27. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, outline note: drawing is not to scale. a3 a a1 e k k b ch d2 e2 l e d 1 2 ddd 3 qfn16-a c
29/32 M41T62/63/64/65 table 18. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm body size, mechanical data figure 28. qfn16 ? 16-lead, quad, flat package, no lead, 3x3mm, recommended footprint symb mm inches typ min max typ min max a 0.90 0.80 1.00 0.035 0.032 0.039 a1 0.02 0.00 0.05 0.001 0.000 0.002 a3 0.20 ? ? 0.008 ? ? b 0.25 0.18 0.30 0.010 0.007 0.012 d 3.00 2.90 3.10 0.118 0.114 0.122 d2 1.70 1.55 1.80 0.067 0.061 0.071 e 3.00 2.90 3.10 0.118 0.114 0.122 e2 1.70 1.55 1.80 0.067 0.061 0.071 e0.50? ?0.020? ? k 0.20 ? ? 0.008 ? ? l 0.40 0.30 0.50 0.016 0.012 0.020 ddd ? 0.08 ? ? 0.003 ? ch ?0.33? ?0.013? n16 16 0.28 1.60 3.55 2.0 ai09126
M41T62/63/64/65 30/32 part numbering table 19. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: m41t 62 q 6 f device family m41t device type and supply voltage 62 = v cc = 1.3v to 3.6v 63 = v cc = 1.3v to 3.6v 64 = v cc = 1.3v to 3.6v 65 = v cc = 1.3v to 3.6v package q = qfn16 temperature range 6 = ?40c to 85c shipping method for soic f = lead-free package (eco pack ? ), tape & reel
31/32 M41T62/63/64/65 revision history table 20. document revision history m41t6x, 41t6x, t6x, t62, t63, t64, t65, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, serial, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, ac- cess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, a ccess, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, access, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interf ace, interface, interface, interface, interface, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interf ace, interface, interface, interface, interface, inter- face, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, interface, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, clock, c lock, clock, clock, clock, clock, clock, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rt c, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, rtc, programmable, programmable, programmable, programmable, programmable, programmable , programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, p rogrammable, pro- grammable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, prog rammable, program- mable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programm able, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, programmable, p rogrammable, pro- grammable, programmable, programmable, programmable, programmable, programmable, programmable, programmable alarm, programmable alarm, programma- ble alarm, programmable alarm, programmable alarm, programmable alarm, programmable alarm, programmable alarm, programmable ala rm, programmable alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, a larm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, alarm, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, inter rupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, interrupt, interrupt, interrupt, interrupt, inter- rupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interr upt, interrupt, interrupt, interrupt, interrupt, interrupt, in- terrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrupt, interrup t, interrupt, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watch- dog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, wa tchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdog, watchdo g, watchdog, watch- dog, watchdog, watchdog, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, switchover, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup, back- up, backup, backup, backup, backup, backup, backup, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write pro- tect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, w rite protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, write protect, industrial, industrial, industrial, industr ial, industrial, industrial, industrial, industrial, in- dustrial, industrial, industrial, vindustrial, industrial, industrial, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, sn aphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, snaphat, soic, soic, soic, s o- ic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic, soic date version revision details november 13, 2003 1.0 first issue 19-nov-03 1.1 add features, update characteristics (figure 2 , 3 , 5 , 10 , 23 ; table 2 , 3 , 9 , 11 , 14 , 17 ) 25-dec-03 2.0 reformatted; add crystal isolation, footprint (figure 25 ) 14-jan-04 2.1 update characteristics (figure 2 , 10 , 25 ; table 1 , 3 . 9 , 14 ) 27-feb-04 2.2 update characteristics and mechanical dimensions (figure 2 , 3 , 4 , 5 , 6 , 7 , 10 , 11 , 12 , 13 , 27 , 28 ; table 3 , 4 , 5 , 6 , 9 , 11 , 14 , 18 ) 02-mar-04 2.3 update characteristics (figure 8 , 9 , 12 ; table 2 , 14 ) 26-apr-04 3.0 reformat and republish 13-may-04 4.0 update characteristics (figure 6 , 7 , 8 , 9 , 25 , 28 ; table 11 , 14 , 15 ) 06-aug-04 5.0 correct diagrams; update characteristics (figure 3 , 4 , 25 ; table 2 , 14 , 16 ) 11-oct-04 6.0 update characteristics (table 11 , 14 ) 18-jan-05 7.0 correct footprint dimensions; update characteristics (figure 3 , 8 , 12 , 14 , 28 ; table 1 , 2 , 5 , 8 , 9 , 11 , 12 , 14 , 15 , 16 , 17 )
M41T62/63/64/65 32/32 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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